1. Field of the Invention
The present invention relates to read/write semiconductor memory devices, and particularly to such devices including both volatile and non-volatile data storage within each memory cell and which are sometimes referred to as shadow RAMs.
2. Description of the Related Art
The design and configuration of semiconductor memory devices frequently must make trade-offs in area, performance, power dissipation, environmental requirements, and volatility. Some memory technologies are high performance, but are volatile (e.g., lose data when powered off), while other technologies are non-volatile but lower in performance. Some non-volatile memory technologies also have limitations on the number of program/erase cycles that may be performed, which limits their suitability for certain applications.
To achieve a high performance non-volatile memory, batteries have sometimes been incorporated into the packaging of otherwise volatile semiconductor memory devices, or included in the system design for such memory device. This adds cost, risks such batteries being discharged too quickly when needed, and may also negatively impact overall reliability.
Another structure for achieving a high performance yet non-volatile memory device combines a high performance volatile memory cell, such as a static random access memory (SRAM) cell with a non-volatile memory cell. The volatile portion of the memory cell may be written and read in the usual manner without limitations as to number of “write” cycles, and the written data may be stored within the non-volatile portion of the cell, such as when power is about to be removed. Subsequently, such stored data may be recalled into the SRAM portion when desirable. Such store and recall operations are frequently carried out for many memory cells simultaneously.
Such combination memory cells are sometimes called “shadow RAM” cells, the implementation of which includes both a fully functional SRAM cell as well as programmable non-volatile data storage elements. Consequently, such memory cells historically are larger than either constituent portion would be alone.